1. Field of the Invention
The present invention relates to a gate array integrated device.
2. Description of the Related Art
In general, since large integrated circuits (LSI) such as complex integrated logic circuits are manufactured in accordance with customers' requirements for a preferred design or development requirements, a small quantity of a large number of different circuits are manufactured. In order to promptly manufacture such circuits at a low cost, a gate array (master slice) method has been suggested.
According to the gate array method, a large number of basic cells are regularly manufactured in advance, and as customers' request, or as development requires, connection masks for unit cells are designed and manufactured, so that the inner connections within the basic cells and the connections therebetween are manufactured. Therefore, since the configuration of the basic cells is common, the manufacturing or development term is reduced, and accordingly, the manufacturing or development cost is reduced.
Note that a basic cell configuration is determined by impurity diffusion regions within a semiconductor substrate having interconnections. Accordingly, this is called a bulk configuration.
The present invention is directed to improving such a bulk configuration.
A prior art bulk configuration consists of a plurality of single column type arrays each of which includes a series of basic cells arranged along the column direction of the device. In such a bulk configuration, however, when unit cells are constructed, the longitudinal length thereof is increased and this causes deterioration of the characteristics of the signal transmission speed and the like. In addition, the connections between the basic cells become long, and it sometimes becomes necessary to increase the connection areas between the single column type arrays, which is disadvantageous from the viewpoint of integration.
To avoid the disadvantages in the above-mentioned single column type array, a bulk configuration has been suggested which includes a plurality of matrix type arrays such as double column type arrays. In a matrix type array bulk configuration, however, it sometimes becomes impossible to arrange the connections for unit cells, since the redundancy of connections for unit cells is small, as will be explained later.